BAD HARDWARE WEEK

US government's Orwellian "error" correcting circuits.
US officials believe bad news from Iraq gets undue coverage.
Mr Rumsfeld said earlier this year that he was concerned by the success of US enemies in "manipulating the media".

Eh, democracy, what is was? War is Peace. Freedom is slavery.
Orwell.

AMD's second source fab starts 65nm production with 90% yield.
Could they start earlier with 65nm? Yes, but no with 90% yield. Now, small AMD core plus 90%
output of working chips will give a lot of cheap AMD processors from its two 65nm fabs. Is it enough to compete with Intel? Yes to grab say at least 33% of the largest, desktop market. To keep 65+% desktop market share, Intel should have at least 3 competitive 65nm fabs continuously on. And it would happen. So, what is actually bad in this hardware story? Intel's further retreat from processor market share. Do you remeber quite recent times when AMD's share was below 10% ?

What a big Opteron class core!. Literally, it is. Shrinked in 65nm it is seems still sized over 300mm2.
AMD estimates that the power consumption of a Barcelona will fit within a 95W thermal envelope. An example cited for a two-socket system, plus memory, plus the chipset, is estimated at about 240W (not counting graphics and storage.) So, Rainier supercomputer will save 50+% on thermal dissipation and cooling expenses due to Barcelona or Deerhound. Oh, by the way, seems that worlds famous me too company has stolen Transmeta low power technology in their new emerald processor named Core Duo. Can we call it more correct Double steal?
I mean, Intel's Core Duo is developed in a country famous for lyars and thiefs, so Transmeta file has a big court chance starting in 2008.

Oh that nasty, Intel -Jewish only Apple. !

Ka'ba, the holy of the holiest Islamic places in Arabic means cube. It is the first place where Allah was worshiped. From the outside it does not look very exciting, due to Islamic ban on pictorial embellishment. It is made of stone blocks. Inside, it is decorated with texts from the holy Qu'ran.

And not with an rotten Apple INSIDE (Intel's TM)

Should Apple lose some 1B of possible customers?
Very likely, after this blatant insult to the whole Islam.

Anyway, Apple is already illuminated enough in the stock options scandal.

The software vendor is one of many high-tech companies having to grapple with the stock options issue. Others include Apple Computer Inc., Broadcom Corp., Sycamore Networks Inc. and Rambus Inc.

Yep really, there is something rotten INSIDE the Apple.

Actually, IBM's SOI will reach some 4,4GHz clock . IBM is now in a systems test and debug phase using the Power6. The CPU will run at speeds between 4-5GHz with a total of 8Mbytes L2 cache and a 75Gbyte/second link to external memory. In addition, IBM will link its Power CPU for the first time to an external embedded controller.The chip can be fully operated at as little as 0.8V.

Interestingly enough , about the same time, AMD's 65nm SOI will start with K8L race towards 3,5Ghz so AMD has kept 3 issues per clock architecture. Intel? Where are you Intel?
Actually, Intel is here.
It is interesting to note that IBM is ramping up frequency for their next generation 65nm Power6 design to over 4GHz in mid 2007 which is what Intel is trying to achieve as well for their 45nm Penryn since it will still take a while for Octo-core to be available.
So, what is the trouble? Well the link quite recently has been sponsored by ... Intel. Do you feel, they are a bit biased?

I think it is highly unlikely that IBM will try to push clock speeds to 6 GHz as the initial Power6 specs suggested a number of years ago. Rather than do this, I think IBM will probably have brought more electronics onto the Power6 core to boost performance and clock will not rise more than 4,4Ghz. If L3 caches are not shrunk and then integrated on the chip with the Power5+, you can bet IBM might do it with the Power6, and then possibly add an external L4 cache to keep those hungry processors fed. So the second die on this Power6 module is L4? Or, still separate 32 MB L3 similar to Power 5+ processor? Probably something in between, at least for dual core packages:
2x4MB large L2 and 32MB L3 on package module.

The only objection of mine is that Power 6 will probably support in a real world insufficient 200 simultaneous operation systems, of 1024 possible. : )

How to sequence 100 people genomes in 10 days to get $10M prize?
Use powerful supercomputer what else. It will enable all 6B people to be sequenced in 600M days, or in only 2M years. However, God needed the same time to create humans as we know today. Still, in a big advantage. What supercomputer manufacturer will take that prize? Until the year 2011 IBM. If has not been awarded until that term, prize goes after to Japan's 10 Pflops babe.

Finally, a truth on bad hardware.
Dell knew for the problem one year ago !

AMD's next architecture will enable Petaflops machines by 2009/10!
If K8L could hit 250TFlops in Cray machines, why not? Amd's next generation Torrenza architecture benefits , gives Cascade future supercomputer computing power over 1 Petaflops. But, hybrid computing is actually what have to excel petaflops systems . By the way, is just that what AMD announces in its next generation processor?

Of course, I don't support Cray's official claim on processors choice Start with best-of-class microprocessor: AMD Opteron, until the claim is proved in many ways. But, ignorants would say: probably Cray has some intristical performance reasons for such a claims.What to say in the end? Lets wait and see. Perhaps the first Petaflops COTS supercomputer system might be someone's else processor based. And what is AMD's official response on Cray's claims?
Known for those under NDA.

Jan Silverman, senior vice president of corporate strategy and business development at Cray, plans to use the Torrenza socket to build a petaflop supercomputer with 24,000 Opteron sockets that will take a custom multithreaded processor, dropping the price per socket from about $127,000 to $10,000 per socket.

Eldorado is a scalable, shared memory, multithreaded computer that uses parallelism to hide memory latencies and full-and-empty bits to support very fine-grain synchronization. The system has no local memory and no processor caches. Each processor supports up to 128 instruction streams feeding a single instruction pipeline.
It combines the Cray/Tera multi-threaded architecture (MTA) processors with the Red Storm network. This new design combines the excellent performance of the MTA on linked structures with the scalability and economy of Red Storm. Nevertheless, the mission is clear. Cross the one petaflop barrier by the end of this decade.
But, IBM might do it with Torrenza + Cell even in 2008 ! Obviously, Torrenza is promising solution for the hybrid architectures of the future.

Cray's Rainier 250TFlops supercomputer, scheduled for 2007/8 is based on AMD's new enhanced core K8L, that should be up to 40% faster than the old K8 one.
System will be based on Opteron equivavalent of Altair Quad core processors named Deerhound. Deerhound chips will naturally use the same 1207-pin socket and will keep inside the same thermal envelope as the new Santa Rosa dual-core Rev F chips, says Vladimir Rozanovich, who is director of AMD's North American commercial business.
Black Widow should be 120TFlops supercomputer sytem with 40TB of RAM and 400 TB of disk space. However, later Rainier's scaling (heat pipe cooled!) should double its peak computing power up to 250 TFlops. The most simple way to do it is to replace dual core Opterons inside with quad core, socket compatible ones, isn't it? Yeah, 125W per processor will not be so easy to cool.
Cray says that the Red Storm design can scale to around 60,000 Opteron cores (11-15K quad cores, or 3K computing nodes?), which should mean Red Storm can scale up to 300 teraflops or more of peak performance, depending on how well the "SeaStar" 3D interconnect, created by Cray to lash Opteron processors and their HyperTransport interconnects together, works.

Some FP instruction references have been found reserved in Rainier performance optimization test tools:

FP_ADD_PIPE 0x40000000
Dispatched FPU ops - Revision B and later revisions - Speculative add pipe ops excluding junk ops

FP_MULT_PIPE 0x40000001
Dispatched FPU ops - Revision B and later revisions - Speculative multiply pipe ops excluding junk ops

Note that AMD K8L = Revision B.
Initially, AM3 socket was planned for the Altair quad cored processors in 3Q2007, with K8L up to 40% more efficient than the old K8, but alas after some problems, AM3 is postponed for 2H2008.
Obviosly, K8L is socket backward compatible, so the only change needed is eventually in BIOS. But, for say AM2+ to AM3 desktop transition, even that would not be required.
Interestingly to note is that if K8L would be announced in 3Q 2007, than that schedule fits nicely with 65nm shrink of K8 core in the first half of the next year. Just not to repeat Prescott failure with simulatenous introduction of new geometry and enhanced core.

And those who don't know history are condemned to repeat it !.
Yeah, K8L will support 48 bit addressing, that means 256TB of memory. Quite enough to keep 250 Tflops Rainier machine running smoothly.


Oooops, K8L clock will run up to 3,5Ghz ?, look at below.
Clock rise of 25% + some 15% boost due to architectural enhancements, that is what gives supposed K8L's 40% performance rise !!
K8L has dynamic I/O bus ! Click on the pictures for higher resolution.

George Bush told the American people the reason we had to start a war in Iraq was because Iraq had Weapons of Mass Destruction. In addition, the President said Iraq had ties to Al Qaeda. Both of these assertions are false.

In a revealing disclosure, Bush aid and the executive director of the 9/11 commission, Philip Zelikow, openly stated the real reason for the war is Israel's security.
The only problem here is that Americans die for Israel!
And Iraq's revenge falls on all the others.