BAD HARDWARE WEEK

Rambus will announce on Wednesday a new Terabyte Bandwidth Initiative (TBI) designed to bring terabyte bandwidth to future many-core architectures. The design places 16 DRAM channels, each operating at 16 Gbps with 4 bytes of data per clock. In theory, the total aggregate memory throughput would be 1,024 Gigabytes (1 Terabyte) available via sixteen separate channels, each of which could be piped directly to a group of multiple cores.
Rambus would like to have TBI memory technology in high volume products as early as 2010 or 2011, though concerns over significant power consumption and heat generation remain a primary focus.
BAD HARDWARE: Old Amdahl's rule relates I/O Tbps bandwidth to TFLOPS of computing power.
1 Tflops is thus quite possible by 2011 on my desk, provided integration of Rambus solution start now, during design of the future processors. However, more energy efficient design alternatives are quite possible about that time frame. Blue Gene /Q supercomputer is too an possible user of the technology.