Thursday, April 14, 2011
3D lithography
Intel researcher Tanay Karnik described floor-planning, power routing, input/output circuits, test and assembly of 3-D processors stacked on DRAM. And Bob Patti, cheif technology officer of Tezzaron Semiconductor, gave a side-by-side comparison of the improvements enabled by 3-D chip stacking, including 40 percent power reduction, a four-times density increase, over 300 percent performance boost, and 50 percent cost reduction.
THIS LINK posted by Joseph Bell : 10:06 AM
