BAD HARDWARE WEEK

It is fairly likely that Intel is designing 64 cores onto the chip, and then — yields being what they are on massive chips — cores with boogers in them will be deactivated and customers will get what they get.
The Larrabee predecessor design used a superscalar x64 core (without the out-of-order execution of Xeons, so akin to the Atom chip in some respects) and a 512-bit vector math unit that could do 16 floating point operations per clock doing single precision math.

BAD HARDWARE: 25% of test failed cores inside chip? Pretty bad. However on the other side, all existing high performance software based on C and C++ will still work. To get functional 64 cores processor you will actually need 80 processors inside MIC (multi integrated cores) chip. Oh, how many Knight Corners for an Exaflops machine? Some 200 000 in 11 nm technology in year 2016-2017. On multichip modules, only 50 000 of them. However, further geometry scaling pace is not quite feasible as it follows from Intel's maps.
But, after hiding fin transistors in their 22nm breakthrough, it is quite possible that Intel hides something more in their sleeves.. Particularly, a cynic would say, if Intel tries to charge $10,000 for one of these Knights that would cost $2B for the Exa cores alone. Hmmm. That might awake you abruptly out the sweet Exa dreams.
Even $1000 per Knight still cost $200M for the cores. On possible power bills is thus a bit premature to speak.
Thus, 100 Pflops knightly goal seems more plausible for now. Not taking in account problems with futuristic machine's huge failure rates.