BAD HARDWARE WEEK

Seems that all modern computer architecture is designed exclusively for physically distant processor.
Whereas data rates of DRAM interfaces have increased by over an order of magnitude over successive generations, the DRAM core frequency has remained relatively constant. Over time, core prefetch size has increased in order to keep pace with improvements in interface bandwidth. These larger prefetch sizes increase the access "granularity" (a measure of the amount of data being accessed), and deliver more data than necessary for applications such as graphics or multi-core computing. Retrieving excess data is inefficient and wastes DRAM and signaling power.

BAD HARDWARE WEEK: What to say for cache hierarchy in processors? Sort of data prefetchers too.