Thursday, October 20, 2011
YARI Simulation and Co-Simulation
The development of YARI has relied extensively on simulation and co-simulation. A simple architectural interpreter was developed and maintained as a golden reference model for the FPGA implementation. Any new feature was first implemented in the architectural simulator and the software was tested there.
However, by far the most important benefit of the interpreter has been its use in co-simulation. By simulating the YARI FPGA implementation in parallel with running the same workload on the interpreter and checking that the two agree on committing operations we can pin-point bugs in the FPGA implementation. The vast majority of bugs have occurred within a handful of cycles of where the divergence was detected.
BAD HARDWARE WEEK:
However, by far the most important benefit of the interpreter has been its use in co-simulation. By simulating the YARI FPGA implementation in parallel with running the same workload on the interpreter and checking that the two agree on committing operations we can pin-point bugs in the FPGA implementation. The vast majority of bugs have occurred within a handful of cycles of where the divergence was detected.
BAD HARDWARE WEEK:
THIS LINK posted by Joseph Bell : 1:09 PM
