BAD HARDWARE WEEK

It’s actually become a fairly common refrain among industry experts. The practice of attaching measurements to chip generations has “been hijacked by marketers to an enormous extent,” one chip-design expert told me. “A lot of it’s really smoke and mirrors,” says analyst Dan Hutcheson of VLSI Research in Santa Clara, Calif. It’s “spin,” he says, that’s designed to hide widening technological gaps between chip companies.

The switch to FinFETs has made the situation even more complex. Bohr points out, for example, that Intel’s 22-nm chips, the current state of the art, have FinFET transistors with gates that are 35 nm long but fins that are just 8 nm wide.
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99% BAD HARDWARE WEEK: Well, seems WE knew. Moore's law has been dead long since 2007,  but we didn't know :)
The term “350 nm node” actually meant something. But around that same time, the link between performance and node name began to break down.