BAD HARDWARE WEEK

Beyond 10nm, IC design and manufacturing costs will be enormous. Only a few chipmakers have the technology know-how and resources to design and manufacture these devices. And so, the industry must collaborate more than ever before, said E.S. Jung, executive vice president of the semiconductor R&D center at Samsung Electronics. “We are doing three nodes at the same time in our R&D center. My target is to approach 1.5nm,” Jung said. “How can we make it happen? We need tools, materials and open innovation. Also, we cannot do it all by ourselves.”



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99% BAD HARDWARE WEEK: ITRS 2013 table is wrong only one year later ! Beside, note the lag between manufacturing node and device size. They are not CLOSE as it was 9 years ago.
Seems that Moore's law  was silently switched in 2005 with a LAW OF DIMINISHING RETURNS !

Manufacturers continue to announce new generations, 45 nanometer, 32 nanometer, 22 nanometer, and coming soon, 14 nanometer, though in fact we have been stuck at 65 nanometer for quite some time. There have been process improvements, but these are incremental improvements. The line pitch remains 65 nanometers. We cannot actually build circuits smaller than we could eight years ago. That these are improvements is no lie, but to label them by a size is a lie. If they had said “second generation 65 nanometer” instead of “45 nanometer”, if they had said “third generation 65 nanometer instead of “32 nanometer”, then they would have been speaking truth, or at least speaking hype rather than lies.


DNA is size of 2,5nm. Isn't the last moment to start thinking differently on future arhictecture and purposes ? What if at nano islands of  2, 5 nm transistor is not needed at all ? And that is only 6 times smaller than current transistors we have.
Simply we could have quantum dot pulses as triggering devices, and that can work at room tempereture for practical devices. Say in Graphene-quantum-dot nonvolatile charge-trap flash memory