BAD HARDWARE WEEK

We could guess at some extent architecture and performance on IBM's Power 9 processor for year 2017 in 10 nm SOI,  after Power 8 in 22nm SOI above.
If history is any guide, then IBM will create Power 8+ chips using a 14 nanometer process in year 2015 with 50%  more processors on the same chip area and Power 9 chips using a 10 nanometer process. This is something that IBM will not, of course, confirm.

Power 9 will mainly differ from Power 8 in HMC 2.0 memory support. Power 9+ in 2019 will implement it in 7 nm SOI, of course if SOI implementatioin  is possible at all in 7 nm. We are at 22 nanometers now, and I think that everybody more or less agrees that silicon will run out of steam in a few technology nodes. We think it will be around 7 nanometers. I believe that the path to 14 nanometers is quite clear, and the path to 10 nanometers is also reasonably clear. I think the point of inflection will come around 7 nanometers, where we will have to think of a replacement for silicon, and at IBM we have been looking at this for quite some time.” Perhaps piezo transistors able to run at 4 Ghz clock but at only 0.15V. Squared, that means 50 times lower power consumption. Or 50 times more SIMULTANEOUS switching than with FIN FETs.
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99% BAD HARDWARE WEEK: However Power 8 is outstanding and impressive itself alone. That is why Power 9 will power Summit supercomputer at stagerring 150 PFlops in the year 2017.
Intel follows IBM Power 8 lead with 6B transistors Haswell-EP 14-18C on the approximately same die area.