Intel's so called high performance nodes are in 18nm ! Low power nodes 16nm and only high density designes inclouding logic in 14nm. High densisty is as you know, for caches, That is why we in so called NEW NODES see first at Intel SRAM wafers.
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99% BAD HARDWARE WEEK: Is Intel's new strategy ( AFTER TICK TOCK) based on interleaved HALF NODES ??
