BAD HARDWARE WEEK

Last fall, Vijay Lund, vice president of server and storage development at IBM's Systems and Technology Group, said that the Power6 chip would have approximately 750 million transistors, would be implemented in 65 nanometer technology, and would use a new kind of chip interconnect called "C4," which at least to my eye is very similar to the socket 1207 interconnect that AMD has created for the future "Rev F" Opteron processors due later this year.

In February, IBM presented a bunch of papers at the International Solid-State Circuits Conference, after it had attained second silicon with the Power6 chip, and said that the chip would be a dual-core processor, just like Power4 and Power5 before it. Which led everyone to wonder what those other several hundred million extra transistors were doing. But because the Power cores have a very sophisticated interconnect that runs at half clock speed, the Power chips have not needed on-chip L3 cache, much less large L2 caches.

In his talk last week, Soltis shed some light on what all of those extra transistors might be doing. He said that the Power6 chips would have "total, three-way redundancy" for many of the components on the chip--and he was not more specific about which features would be redundant.
Soltis was not, of course, more specific about how this triple redundancy might be implemented. It is hard to imagine that he literally meant that IBM had put six Power cores on the chip, but this is quite possible even if it does sound like overkill.

6 Power6 cores on the same chip? Well, this is exagerrated. But, what about 2 cores with one single integer and two FPU units at each core? Something that is rumored to be on AMD's K9 Core Revision G in 2007? About the same time when Power 6 will be available? Finally I understand why Intel currently invests $10B to keep sinking Itanium afloat until the year 2008. Then should finally emerge a really new generation Nehalem architecture that will send Itanium deep below the floating line. Forever.

Intel uses lowe geometries for caches.Rusu said Intel did not use multiple transistor threshold voltages in the cache--a common power-saving technique--for Tulsa; instead, it made "massive use of longer-channel-length transistors." The transistors run slower but incur 3x less leakage, he said.

McCredie said IBM employed three threshold voltages and tuned the channel lengths in the Power6 to achieve a trade-off between leakage and performance.

Some architecture details are here.

Thus, IBM too optimized parts of Power processor that leak the most. That is actually Power6 high clock secret in 65nm. AMD did the same. But Intel couldn't do that even with their 90nm bulk silicon for high clock, so Prescott and Tejas failed. That is the main difference.

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