Wednesday, November 29, 2006

AMD 65nm K8L Deerhound in last detail !


On August 15, 2006, at the launch of the first Socket F(1207) dual core Opterons, AMD announced that the firm has reached the final design stage (i.e. Tape-out) of K8L quad-core Opterons, codenamed Deerhound. This will now go to the test and validation stage; and will be available for samples in the next several months. Please note peak 100 Amperes of needed power supply. At 1,25V voltage applied that gives 125Watts of Deerhound's TDP.
The K8L core will also have a 32-byte prefetch (versus 16 right now), 48-bit addressing with 1GB pages.
Each of the cores thus will access entire 1GB of memory directly ?
On the other side, I am not sure is it revison H or revision B.



Let me in the end to citate distinguished TheInq journalist:
Anyone want a HyperTransport-based quad-socket quad-core 45 nm IntelCore server, combining the superb new IntelCore execution with liberated system bandwidth potential? I sure wouldn't mind one. ยต

Well, what about original AMD quad socket Deerhound? Anyone want it? However, sometimes original is still better than the me too copy. :)
Especially in 2007 , when Intel will be still without serious competition to AMD's HT.
Actually, without any kind of hypertransport, that will remain only distant subject of Intel's wishes until sometime in 2008. Briefly, Intel has supposedly Ferari engine for performance race with AMD, but seems without adequate bus running tyres. :)
Not after me ,but according to PathScale, AMD's HyperTransport interconnect provides greater overall bandwidth and scalability over anything else currently available.


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