BAD HARDWARE WEEK

IBM system p6 570 server equipped with 8 - core SMP implemented Power6 processor chips each initially clocked at 4,7 GHz with L2 Cache of 4 MB and L3 Cache of 32Mb.

Each Power6 chip has two cores, and each core will have its own dedicated 2 MB L2 cache memory. With the Power4 chips, IBM had 1.44 MB of shared L2 cache for the two cores on the chip, and with the Power5 design, IBM increased the shared L2 cache to 1.9 MB. As with the Power5, each Power6 core can have a 32 MB L3 cache assigned to it. The Power6 chip also includes two memory controllers on chip as well as an L3 memory controller and an L3 directory cache. IBM is allowing one or two memory controllers to be turned on, as necessary in the system design, and they can be configured to run at full or half width, too. The Power6 chips will come with L3 cache in three different configurations--those without L3 cache, those with the L3 cache on the module (as was done with the Power4 and Power5 chips), and those that have the L3 cache off the module.

AIX 5L roadmap is based on Power architecture until 2014. However, I couldn't find similar OS support for Intel's Itanium. :)
Power6 solved leakage problems by 90-65nm optimized implementation.
But, the Power6 chip also includes a two-tiered memory coherency protocol that has significantly lower latencies compared to the Power5. That well explains architectural improvements behind the achieved 4,7Ghz clock rate.