BAD HARDWARE WEEK

Pure Nehalem core is 1,5 time bigger ! Seems due to additional 110M transistors in integrated controller and Quick Path. However, implemented in 32nm in 2009 it should be only 0,75 die area of forthcoming 45nm Penryn.

P.S. I got one comment on Opteron. Why its HT3 is related with DDR3? Actually it might work even with advanced DDR2, but don't forget that any future design of low latency DDR3 is not and can't be supported with current, only initial BA release of Opterons. That is the problem when you have integrated memory controller, and Intel will start facing the same one problem after the Nehalem launch. I guess the next question is why we need low latency DDR3 ?. Well, DDR3 is faster than DDR2, but its relative speed introduces one additional bothering problem called latency - the time needed for any signal to arrive. The problem is inherently related with restricted speed of electron moving, close to famous number c. That problem can't be of course ever solved by our current knowledge, but might be elegantly bypassed by advanced circuit design, though again alas, not completely and not forever.
I wouldn't guess on forthcoming B2 Opteron release, but current BA release actually might be its weaker though volume production ready version. Available the earliest in November this year, but more likely in Q1 next year. Yeah, yeah, memory prefetching alleviate the latency, but 4 and 8 core memory prefetching, are you serious?