BAD HARDWARE WEEK

MCM based, Montreal processor are actually two 45nm Shanghais on a module, each with 6MB of L3. Of course, G3MX memory buffer extenders enables 16 DDR3 registered memory modules. That is actually deployment of HT 3.o and memory unganging, so each of 8 cores has its own memory channel or two. Actually we have that way 8 independent servers, without memory congestion. That will make virtualisation fly.
Thus, this is why you should sign NDA with AMD? Bah. Intel should be ready for that event, though I hope a bit better than the last time during the Montreal race (see the pic below).