BAD HARDWARE WEEK

In a nice presentation, Penryn main architect explains its main benefits : faster bus plus bigger cache.
However, seems that he missed to stress one very important thing: Penryn's TDP of 150W.

He forgot too that with faster buses latency rises too, so that is why Penryn L2 is more associative and its cache is bigger. "so they aren't really hiding or controlling latency, just making it less important by preloading data so latency is basically "hidden" since the data is already fetched."
And that made Penryn's power consumption huge.Intel's shows obvious and inherent inability to make things any better before the Nehalem appearance, in a year or so.