Wednesday, December 10, 2014

Chip shrink will continue: EUV double patterning for 7nm logic

NXE:3350 is EUVL scanner for 14nm requiring commercial throughput of 1500 wafers per day. There is no 7nm logic without EUVL double patterning or ArFi quadruple patterning. Best should be combination EUVL double patterning with the rest of metallization using triple patterning ArFi.
99% BAD HARDWARE WEEK:10 nm logic could be made experimentally with single patterning EUVL and quadruple patterning ArFi. DRAM without any problem in 2017 with 14nm halh pitch. As you can see from the diagram above.
The ultrathin dielectric layers of Samsung latest DRAMs are composed of atomic materials, aka atomic layer deposition.
Retrospection: In 2006 we have had first EUVL advanced development tool. Are EUVL deadly late after 11 left years in 2017. If not able to produce even DRAMs in 2017 EUVL is definitely dead in the vacuum ( please take in account that EUVL is solely vacuum and not immersion technology like ArFi). Why ? Because Apollo Mon program was completely realized in 11 years. Russian Moon technology was dead born. Thus, let us see EUVL FLYING in the next 3 years, or ...face serious consequences in processor and component advancement stall.

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