Monday, June 22, 2015

Intel’s 28-core Xeon ‘Skylake’ CPUs to support 6TB of DRAM, LGA-3467 ?

The “Purley” platform will be Intel’s biggest server platform advancement in many years, when the world’s largest chipmaker rolls it out in 2017. Intel’s “Purley” will be a highly-configurable platform designed for enterprise, cloud, HPC [high-performance computing], storage and network applications. Intel “Purley”-based supercomputers are expected to finally hit ExaFLOPS performance late this decade.

Intel Xeon “Skylake”: 28 cores, 6-channel DDR4 memory, Omni-Path fabric
Intel will release three different versions of Xeon processors for its “Purley” platform targeting different applications two years from now – “Skylake-EP”, “Skylake-EX” and “Skylake-F” – according to a report from CPU World. The new chips will feature up to 28 cores based on the “Skylake” micro-architecture with AVX512 instructions and Hyper-Transport technology, up to six DDR4 memory channels (up to two 2400MHz DIMMs per channel are supported, i.e., up to 768GB of DDR4 memory per socket without SMB), up to 48 PCI Express 3.0 lanes as well as two or three UPI channels per socket.

Intel Xeon “Skylake-EX” processors will be designed for high-performance and mission critical machines with two, four or even eight sockets, which means that they will feature up to three UPI links. The processors will introduce new RAS [reliability, availability, serviceability] features such as Instruction Retry (pipeline error protection for integers), Advanced Error Detection and Correction as well as Adaptive Dual Device Data Correction, to make next-gen high-end servers even more robust. According to previously released unofficial information, Intel’s forthcoming expandable processors will support four times higher memory capacity (compared to today’s chips) thanks to “Apache Pass” scalable memory buffer (SMB), which means up to 6144GB (over 6TB) per socket, or up to 24.576 GB of DDR4 RAM per 4S machine. The “Skylake-EX” chips will have TDP of up to 165W.

Xeon “Skylake” processors will use the new socket P0 and will feature flip-chip land-grid array packaging (FC-LGA) with up to 3467 contacts. The final amount of pins to be used is unclear today, but according to unofficial information, it will exceed 3000 balls.


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