BAD HARDWARE WEEK

Truth is just as BADHARDWARE stressed by SPEC_base_rate2006 tests: Intel's architecture sucks.
However, "distinguished" The Inq's journo sucked himself after months and months of bullshits
on invincible Intel. Barcelona Architecture is so much superior towards Intel's that AMD should be merciful towards Intel ! In my opinion why still there is no wider support for HT3 is actually a lack of accepted DDR3 and advanced lower delay DDR2 memories, that should feed Barcelona inherent huge bandwidth appetite. However, situation might be better for Intel, but only AFTER introduction of the new generation architecure called Nehalem in 2H 2008 (see its functional diagarm at the pic below).


Until then, we will have the following situation at Intel:
Intel® Smart Memory Access
Intel® Smart Memory Access improves system performance by optimizing the use of the available data bandwidth from the memory subsystem and hiding the latency of memory accesses.

Intel Smart Memory Access includes an important new capability called "memory disambiguation," which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed
- http://www.intel.com/technology/arch...icro/index.htm

Smart Memory Access: To help the processor work at peak efficiency, Intel chips have long had the capability to speculatively re-order the flow of incoming instructions, such as to load data for instructions before that data's needed. A challenge, though, has been to preload data before all previous store instructions are executed, because the chip doesn't know if there are dependencies for that particular data. With the Intel Core microarchitecture, the processors have new algorithms that help them determine when it's useful to preload data—and to quickly detect when that preloaded data has been changed, and must be reloaded into the cache.

Part of this new mechanism includes more advanced prefetchers. With NetBurst and Pentium M, there were two prefetchers, one for the L1 cache and one for the L2 cache. With Intel Core, there are four prefetchers, two for the L1 and two for the L2. A benefit of all this is that the processor is going to be less likely to sit around in a wait state when there's a cache miss; the smarter memory access and more efficient prefetch mechanism will keep the instruction pipeline and caches full, and full with the right stuff.
- http://www.devx.com/Intel/Article/30831

Let me make a brief:
"so they aren't really hiding or controlling latency, just making it less important by preloading data so latency is basically "hidden" since the data is already fetched."

And nothing will be much better until Intel's toc in 32nm in 2009. Poor Intel.