Sunday, September 30, 2007
Japan to develop next generation network in 2015
The group will be established in November by the government-affiliated National Institute of Information and Communications Technology and private companies, the leading business daily Nikkei said.
It will aim to develop and commercialise in around 2015 a network that can transfer data at 10 gigabits per second, 10 times faster than the next-generation network due to be launched in Japan this year, the report said.
The optical network would allow as many as 100 billion devices to access it simultaneously and still enjoy extremely fast data-transfer speeds, the report said.
Currently, IP v4 can't support without NAT more than 4 Billion networked devices. Here is US version of Japan future network.
AMD's K10 will shine in 45nm
Until then, yet another year with $1B losses?
'We believe the company's late Barcelona introduction and disappointing early performance are an early indication of a bad marriage of process technology and design that will be hard to fix before a move to 45-nm is required,'' said analyst Doug Freedman of American Technology Research Inc., in a new report.
Thus, analysts think Barcelona is not genuine design for 65nm? However, when AMD's 45nm should be finally ready, Nehalem in 45nm would be ready too? Seems like a big gamble. Anyway, only PC users will be the winners.
'We believe the company's late Barcelona introduction and disappointing early performance are an early indication of a bad marriage of process technology and design that will be hard to fix before a move to 45-nm is required,'' said analyst Doug Freedman of American Technology Research Inc., in a new report.
Thus, analysts think Barcelona is not genuine design for 65nm? However, when AMD's 45nm should be finally ready, Nehalem in 45nm would be ready too? Seems like a big gamble. Anyway, only PC users will be the winners.
AMD promotes Athlon 64 2000+ that consumes only 8Watts
At 0.85 V and 1Ghz clock. Nice singlecore for handhelds.
And 2Ghz A64 3100+ at 25W. Nice for notebooks.
Please note that 2 times higher clock means 3 times higher TDP.
Not linear, as expected. 4 Ghz A64 would consule only 75W?
3Ghz only 45W? Dual core at 3Ghz would consume 89W?
Seems a lot of space for scaling at AMD. Because Intel's 45nm
already knocks at its doors, see below.
Intel's Dual Core in 45nm , January 2008 | |||||
E8500 | 3.16GHz | 6MB | 1333MHz | - | $266 |
E8400 | 3.00GHz | 6MB | 1333MHz |
| $183 |
E8300 | 2.83GHz | 6MB | 1333MHz | - | - |
E8200 | 2.66GHz | 6MB | 1333MHz |
| $163 |
Big Brother sequel
The City of Chicago is developing a futuristic video surveillance system designed to scan city streets looking for everything from bombs to traffic jams.
And I would add: suspicious people when elections perhaps soon prove to be obsolete.
In 1984, Winston Smith lives in London which is part of the country Oceania. The world is divided into three countries that include the entire globe: Oceania, Eurasia, and Eastasia. Oceania is a totalitarian society led by Big Brother, which censors everyone's behavior, even their thoughts.
Perhaps Oceania today is Pacific rim ? Eurasia is widened EU. And Eastasia is India, Pakistan, Islamic countries, Africa and perhaps China.
Everywhere surveillance (girl).
The Godfather - sequel 4 : Mafia revenge
50 years ago, Sputnik changed the world
50 years ago, Sputnik changed the worldLook at its launch video here.
Actually, as described by the former scientists, the world's first orbiter was born out of a very different Soviet program: the frantic development of a rocket capable of striking the United States with a hydrogen bomb.
Using mobile towers, Sprint this year signaled satellites to provide cell phone service to emergency workers after a tornado in Greensburg, Kan., ripped that area’s communications infrastructure to pieces.
All told, the U.S. Air Force counts some 6,000 satellites launched into space, at the behest of more than four dozen countries, since Sputnik. About 3,200 of those satellites continue to orbit — including two that deliver XM Satellite Radio.
Their names?
“Rock” and “Roll.”
By the numbers
5,958 Total man-made satellites — from puppy-toting capsules to the things that beam driving directions to your dashboard — that orbited the planet
5,958 Total man-made satellites — from puppy-toting capsules to the things that beam driving directions to your dashboard — that orbited the planet
9,341 Pieces of space junk loitering above the atmosphere
1 in 3 Chances that a satellite or scrap of space junk is American-made
352 Lead in orbiting satellites the former Soviet Union has over the United States
Spawn of Sputnik
3,204
Number of satellites circling Earth today
2,754
Number of objects launched into the sky that have fallen back to Earth — including Skylab, the space shuttles and thousands of satellites you never knew were aloft.
A lot of bad hardware floating around, isn't it?
Saturday, September 29, 2007
Barcelona B2 sucks?
I am not sure at what stepping Barcelona is now, but I just did some testing with the B2 stepping at 2.5 GHz, and it seems that contrary to what some people have been claiming, that this stepping has actually a slightly slower northbridge.
BA BArcelona revision is B1 with the northbridge fix. FWIW they found the erratum after B2 taped out.
So, lab test with B2 enginnering sample will show slower Northbridge. We will have to wait B2A production release? In the meantime please note slowdowns that make AMD's strange IMC ratios.
What about Intel's Nehalem on the same topics?
The north bridge strategy will stay active in CSI era as well. Chipzilla will not take AMD's route and simplify chipsets to a point where "chipset" is actually a single chip, but will keep current two chip configuration?.
Nehalem comes with CSI: (Common System Interface), but it will be connected to 65nm north bridges that will spot additional memory controller. It is quite obvious that FB-DIMM controller will be removed/disabled for the desktop and notebook part, and chipset will be the one that will provide DDR-2/DDR-3 support. This also applies to servers with registered ECC DDR2 memory.
BA BArcelona revision is B1 with the northbridge fix. FWIW they found the erratum after B2 taped out.
So, lab test with B2 enginnering sample will show slower Northbridge. We will have to wait B2A production release? In the meantime please note slowdowns that make AMD's strange IMC ratios.
What about Intel's Nehalem on the same topics?
The north bridge strategy will stay active in CSI era as well. Chipzilla will not take AMD's route and simplify chipsets to a point where "chipset" is actually a single chip, but will keep current two chip configuration?.
Nehalem comes with CSI: (Common System Interface), but it will be connected to 65nm north bridges that will spot additional memory controller. It is quite obvious that FB-DIMM controller will be removed/disabled for the desktop and notebook part, and chipset will be the one that will provide DDR-2/DDR-3 support. This also applies to servers with registered ECC DDR2 memory.
Barcelona delay was actually good?
Yeah, good for Intel.
Without jokes, it was good even for AMD. Desktop mArket simply isn't yet ready for 4 cores.
Currently only 2% of it. Thus, all was a gamble.Howeever, seems that 3 cores might be accepted in Q1 2008.
So, let me point to Phenom X3 as a possible success.
US dollar to plunge
According to Mike Swanson, "the accumulation of debt in the United States cannot continue much longer. In the last century the ratio of debt to GDP hovered between 120% and 160%. In 1929 debt rose to 260%. Now the ratio of debt to GDP is at a mad 300% and has been growing over the past year. Something has to give."
Oil and gas are at all-time highs while metals such as silver are up more than 25% in 2004 and gold up 50%."
The Bulletin of the Atomic Scientists created the famous "Doomsday Clock," whose hands they move forward and backward as they see the dangers of nuclear war ebb and flow. A few years ago they moved the hands of the clock seven minutes to midnight, a setting higher than it was at the end of the cold war, because the US had rejected a series of arms control treaties while terrorists had been seeking to acquire nuclear weapons.This is the 24th hour for US dollar. I'd say we are 15 minutes away from midnight on the dollar clock.
Friday, September 28, 2007
AMD Torrenza and overall IT power consumption accelerate
Industry-leading AMD technology partners including HP, ACTIV Financial, and RapidMind, among many others, are delivering market-ready “Torrenza” solutions today in which discrete accelerators and customer-specific silicon enhancements combine to create energy-efficient, high-performing and scalable solutions for accelerated computing environments.
However, overall IT power consumption is on the rise too.
I hope AMD's low power strategy would alleviate or even cancel it. Or global warming is allegedly unstoppable. Just as IT industry is.
However, overall IT power consumption is on the rise too.
I hope AMD's low power strategy would alleviate or even cancel it. Or global warming is allegedly unstoppable. Just as IT industry is.
Thursday, September 27, 2007
NAND IO-drive breakes 1TB limit in 2008
PCI EXpress X4 is used. Transfer speed is close to 1GByte/sec. Thus, this 640GB drive above will be read in some 11 minutes ! How long we have waited until HD brake 1TByte limit? Too long. However, enormous demand for NAND chips made ie. Toshiba sold out all of its NAND chips until December this year
Mark 666 tattoo again
Unfortunately last week someone broke in and stole 6 computers, including the big iMac at the front counter. You know... the one everyone uses for Flickrbooth fun?
They took with them four laptops and our two iMac's. We have the crime on tape, but weren't able to capture a high res. image.
This morning Kris Krug was checking one of Workspace's Flickr accounts and noticed something strange... a photo of a tattooed man, "me", uploaded to the account. Sirens started to go off and everyone soon realized that this was more than likely the thief (or one of them). He was using the stolen computer to upload photos of himself to Flickr without thinking to log into his OWN Flickr account. Busted.
UPDATE 09/25: This photo (as of this morning) has 199,743 views on Flickr, thousands of Diggs, was featured at the top of the 6 o'clock CTV news in Vancouver last night and is in the Globe and Mail this morning. Talk about coverage!
UPDATE 09/26: The man in the photo has turned himself in to Victoria Police, according to an article in today's Vancouver Sun.
Workspace is incredibly happy to see the man step forward. He claims to have bought the computer from a friend of a friend, but returned the iMac and hopefully has more information that could lead to the capture of these criminals.
Intel screwed up with FB-DIMM, Nehalem will use DDR3
Finally, a truth on bad hardware. However, AMD has already DDR3 support incorporated in Barcelona chip , though as BAD HARWDARE founds switched off. For now. And reportedly, Nehalem should be a great success. Why not BArcelona? Now. However, in the future, let me notice, 16 unganged banks of HT3 at Shanghai relatives will sport 16 x 2GB = 32 GB of DDR3. With 4GB memory modules that will be hefty 64 GB.
By the way, DDR3 will start to dominate over DDR2 only in 2009. So, why bother with DDR3 support?
John: DDR3 technology itself is optimized for clock rate rather than for bandwidth. And our lab testing results back this up. Not to say that latency is not important, of course – that’s why we test our 1800MHz part at 7-7-7-20, which I believe is the lowest latency currently being offered at anywhere near this clock rate.
El Pais: How Iraqi bloodshed was actually designed
Texas and California, go ahead, you got a nice El Pais sequel readings in Spanish. Give it US translated, please. Sort of a new crusade? Read here.
Wednesday, September 26, 2007
45nm Penryn and Nehalem
Pure Nehalem core is 1,5 time bigger ! Seems due to additional 110M transistors in integrated controller and Quick Path. However, implemented in 32nm in 2009 it should be only 0,75 die area of forthcoming 45nm Penryn.
P.S. I got one comment on Opteron. Why its HT3 is related with DDR3? Actually it might work even with advanced DDR2, but don't forget that any future design of low latency DDR3 is not and can't be supported with current, only initial BA release of Opterons. That is the problem when you have integrated memory controller, and Intel will start facing the same one problem after the Nehalem launch. I guess the next question is why we need low latency DDR3 ?. Well, DDR3 is faster than DDR2, but its relative speed introduces one additional bothering problem called latency - the time needed for any signal to arrive. The problem is inherently related with restricted speed of electron moving, close to famous number c. That problem can't be of course ever solved by our current knowledge, but might be elegantly bypassed by advanced circuit design, though again alas, not completely and not forever.
I wouldn't guess on forthcoming B2 Opteron release, but current BA release actually might be its weaker though volume production ready version. Available the earliest in November this year, but more likely in Q1 next year. Yeah, yeah, memory prefetching alleviate the latency, but 4 and 8 core memory prefetching, are you serious?
AMD should be merciful towards Intel !?
Truth is just as BADHARDWARE stressed by SPEC_base_rate2006 tests: Intel's architecture sucks.
However, "distinguished" The Inq's journo sucked himself after months and months of bullshits
on invincible Intel. Barcelona Architecture is so much superior towards Intel's that AMD should be merciful towards Intel ! In my opinion why still there is no wider support for HT3 is actually a lack of accepted DDR3 and advanced lower delay DDR2 memories, that should feed Barcelona inherent huge bandwidth appetite. However, situation might be better for Intel, but only AFTER introduction of the new generation architecure called Nehalem in 2H 2008 (see its functional diagarm at the pic below).
Until then, we will have the following situation at Intel:
Intel® Smart Memory Access
Intel® Smart Memory Access improves system performance by optimizing the use of the available data bandwidth from the memory subsystem and hiding the latency of memory accesses.
Intel Smart Memory Access includes an important new capability called "memory disambiguation," which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed
- http://www.intel.com/technology/arch...icro/index.htm
Smart Memory Access: To help the processor work at peak efficiency, Intel chips have long had the capability to speculatively re-order the flow of incoming instructions, such as to load data for instructions before that data's needed. A challenge, though, has been to preload data before all previous store instructions are executed, because the chip doesn't know if there are dependencies for that particular data. With the Intel Core microarchitecture, the processors have new algorithms that help them determine when it's useful to preload data—and to quickly detect when that preloaded data has been changed, and must be reloaded into the cache.
Part of this new mechanism includes more advanced prefetchers. With NetBurst and Pentium M, there were two prefetchers, one for the L1 cache and one for the L2 cache. With Intel Core, there are four prefetchers, two for the L1 and two for the L2. A benefit of all this is that the processor is going to be less likely to sit around in a wait state when there's a cache miss; the smarter memory access and more efficient prefetch mechanism will keep the instruction pipeline and caches full, and full with the right stuff.
- http://www.devx.com/Intel/Article/30831
Let me make a brief:
"so they aren't really hiding or controlling latency, just making it less important by preloading data so latency is basically "hidden" since the data is already fetched."
And nothing will be much better until Intel's toc in 32nm in 2009. Poor Intel.
However, "distinguished" The Inq's journo sucked himself after months and months of bullshits
on invincible Intel. Barcelona Architecture is so much superior towards Intel's that AMD should be merciful towards Intel ! In my opinion why still there is no wider support for HT3 is actually a lack of accepted DDR3 and advanced lower delay DDR2 memories, that should feed Barcelona inherent huge bandwidth appetite. However, situation might be better for Intel, but only AFTER introduction of the new generation architecure called Nehalem in 2H 2008 (see its functional diagarm at the pic below).
Until then, we will have the following situation at Intel:
Intel® Smart Memory Access
Intel® Smart Memory Access improves system performance by optimizing the use of the available data bandwidth from the memory subsystem and hiding the latency of memory accesses.
Intel Smart Memory Access includes an important new capability called "memory disambiguation," which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed
- http://www.intel.com/technology/arch...icro/index.htm
Smart Memory Access: To help the processor work at peak efficiency, Intel chips have long had the capability to speculatively re-order the flow of incoming instructions, such as to load data for instructions before that data's needed. A challenge, though, has been to preload data before all previous store instructions are executed, because the chip doesn't know if there are dependencies for that particular data. With the Intel Core microarchitecture, the processors have new algorithms that help them determine when it's useful to preload data—and to quickly detect when that preloaded data has been changed, and must be reloaded into the cache.
Part of this new mechanism includes more advanced prefetchers. With NetBurst and Pentium M, there were two prefetchers, one for the L1 cache and one for the L2 cache. With Intel Core, there are four prefetchers, two for the L1 and two for the L2. A benefit of all this is that the processor is going to be less likely to sit around in a wait state when there's a cache miss; the smarter memory access and more efficient prefetch mechanism will keep the instruction pipeline and caches full, and full with the right stuff.
- http://www.devx.com/Intel/Article/30831
Let me make a brief:
"so they aren't really hiding or controlling latency, just making it less important by preloading data so latency is basically "hidden" since the data is already fetched."
And nothing will be much better until Intel's toc in 32nm in 2009. Poor Intel.
Intel announces the prices for unannounced products ?!
The Conroe (and Kentsfields) have taken the performance crown from AMD and are currently on a roll but these will not be battling AMD's upcoming Phenom processors as Intel is preparing the new 45nm-built Yorkfield and Wolfdale CPUs. The models ready to be rolled out in Q4 2007 and Q1 2008 have already been revealed but what was unknown was the sum Intel will want for its updated line-up. Now, with the exception of the lonely dual-core E8300, the rest of the 45nm pack is priced and can already start causing AMD an extended headache.BAD HARDWARE comment: Extended headaches? Have taken performance crown? WHAT A B...T !
AMD's server chips are lower priced . Even now, not to mention Q1 2008. You know, 12MB caches is not easy to manufacture, even in proposed 45nm. Thus, who will have headaches? Beside, AMD will boost its Phenom core clock up to 2,6 Ghz thus talking on performance advantage in desktop using Core 2 clock of 3Ghz is really ridiculous. Just opposite, Intel will be in headaches, both performance and price.
In the name of the Lord
Something is seems suspicious here. Looking for a 666 mark tattoo at nun's thigh?
Tough we are living in the country of freedom, 666 is not quite suitable.
Tuesday, September 25, 2007
Quad core Opteron for $236
AMD Opteron Quad Core 2344 HE CPU OS2344PAL4BGE, 1.7GHz, Socket F (1207), 1000MHz HT, 2MB L2 Cache
Features & Specifications: Processor: Third-Generation AMD Opteron. Model: 2344 HE. OPN PIB: OS2344PAL4BGE. Revision: BA. Core Count: 4. Core Speed (Mhz): 1700. System Bus Speed (Mhz): 1000. Voltages: 1.15 V. Max Temps (C): 55oC to 71oC. Wattage: 55 W (ADP). L2 Cache Size (KB): 2048. L2 Cache Speed (Mhz): 1700. L3 Cache Size (KB): 2048. CMOS: 65nm SOI. Integrated Memory Controller Speed (Mhz): 1400. Socket: Socket F (1207).Comment: Not so long time ago, for only $236 you couldn't buy even a quarter of a decent processor.
3 cores for $180 ?
Details of Intel's future CSI - QuckPath processor interface
Monday, September 24, 2007
Parallel universes exist - study
Oh, when we only could use programmers from those parallel universes to help in optimizing forthcoming, otherwise mainly useless 4 , 8 and 16 cored processors.
Dresden fights for AMD's new 4X fab
Now, fighting two cities: New York and Dresden for AMD's confidence tells something on confidence in AMD? I repeat, confidence.
Right?
Right?
Sunday, September 23, 2007
Intel lays off 9200 more !
Together with last year fired 12200 it is some 21400 out in a two years. And that is the real cause of Intel's recent financial surplus. However, 9 years more of those kind successes, and Intel will completely remain out of working force !!
Can we call this process in computer architecture : working force bottleneck? Let me remind you,
that stuff cut is direct consequence of the price war with AMD.
Intel's layoff of 1200 this August is only a start. And this way Intel is preparing for bigger market share?
Google goes under the sea
Google goes under the sea by 2009. Actually, under the Pacific Ocean.
Google's infrastructure ambitions are no secret. The company has committed substantial expenditure on dark fibre and a network of data centres across the United States, and also recently indicated its interest in bidding for new 700MHz spectrum allocations there.
Thursday, September 20, 2007
Oh Big Brother, you fly so high
The results of an investigation by the Identity Project show that DHS is actively collecting information on what Americans read, with whom they associate, and the ethnicity of individual American travelers. DHS is also actively acquiring the travel records of Americans that document non-US travel, e.g., intra-European flights.
Nehalem is 8 cored ?
Nehalem is 8 cored ?
Nehalem will be a native 8 core CPU and this is exactly what Pat Gelsinger said to Huan from Chilehardware.
There are the following possibilities:
1. MCM design used like today, what is the most likely outcome, when 2 CSI interconnections will be used for the links between the two 4 core dies, and you can see one here.
2. Nehalem will be late in 2009 and will be made in 32nm, that enables it to be native 8 core product. Let me remind you that AMD in Q1 2009 will have MCM 8 core product named Montreal (after F1 racing town), so this option has some sense.
3. Or ... simply both.
BADHARDWARE verdict: No, Nehalem shouldn't be natively 8 cored. Westmere in 32nm should be Intel's first native 8 cored product. And Nehalem might have 8 core interface support switched off. However, if AMD would have 730M transistors like Nehalem, instead of its current 473M transistors in Barcelona, it might have 8 native cores. In 2009, Intel will sell Nehalem processors with eight cores on a single slice of silicon.
However, AMD's dark side answer we will not wait more than September 25th this year. What the hell it is?
Intel - AMD brake !
Intel won't support AMD's SSE5
But we all "know" that the Intel is leader in the field, and trend setter??. Does that mean that AMD goes ahead alone?
But we all "know" that the Intel is leader in the field, and trend setter??. Does that mean that AMD goes ahead alone?
Wednesday, September 19, 2007
Linux kills innovation, IBM MS's Office ??
Innovation? So, EU fined MS with some $600M, after that inherent inability. And IBM gives Lotus Symhony for free, being long time basically unable to fight in the field.
Intel's Nehalem
You can see 4 x 2MB L2 placed at the bottom of the Nehalem picture. Let me not that AMD will run much earlier the same with 6 MB L3. Thus, Nehalem doesn't seem like a Shanghai killer to me.
Please register now !
What has happened to the speech I/O computer interface?
Will the new SALT speech technology give developers a better alternative for input and output on wireless Web devices? Well, after some 20 years hearing the field, you should take all the claims with a grain of SALT.
Farewell Mr. President
The worst President ever? I don't agree. He is double the worst President ever. However, does that pesky fact speaks more on his voters (supporting him now 36%) than on himself?
Tuesday, September 18, 2007
Intel's 45nm stars
However, by then, AMD will be finally ready with B2 , highly scalable K10h revision.Monday, September 17, 2007
AMD prepares new chip formula for Q1 2009 race: Montreal
MCM based, Montreal processor are actually two 45nm Shanghais on a module, each with 6MB of L3. Of course, G3MX memory buffer extenders enables 16 DDR3 registered memory modules. That is actually deployment of HT 3.o and memory unganging, so each of 8 cores has its own memory channel or two. Actually we have that way 8 independent servers, without memory congestion. That will make virtualisation fly.Thus, this is why you should sign NDA with AMD? Bah. Intel should be ready for that event, though I hope a bit better than the last time during the Montreal race (see the pic below).
First Barcelona emerges at the shops, Intel in panic gives Nehalem details
1.9 Ghz type 2347. I wonder why Intel gives Nehalem details if the Barcelona, let me quote "distinguished" hardware sites, is still "worthless". Please note that I didn't quote "late", though it took so many attention at the distinguished shares market analytics.
Intel in panic gives Nehalem details: DDR3, 8MB L2, integrated memory controller, Quick paths interconnection, LGA 1366 socket, etc. However, let me suggest that Intel's new architecture and AMD K10 are fundamentally different architectures regarding the size of L2. K10 solves all quad core communications issues in cache, and Intel will do it a bit different, so it needs huge (and thus slow) L2 caches. By the way, I wonder why Intel gives up now from its long time established corporate strategy not to talk about still unannounced products? Or this man Goto has some Japan - Santa Clara quantum entaglement capabilities, what is on the other side, still premature.
Big Brother counts: 1,2, 3, 4, 5
The US and UK governments are developing increasingly sophisticated gadgets to keep individuals under their surveillance. When it comes to technology, the US is determined to stay ahead of the game.
Well, eat this LATEST MEDIA DEFENDER SCANDAL.
Saturday, September 15, 2007
AMD's count up: 1, 2, 3
Actually, people have manufacturing problems and low yields and there is a simple solution. When you bake 3 cores, at least two of them will be likely functional. They will pass the test and might be sold as two cores on a chip. That will cost you more 50% of silicon are than on dual core baking but if AMD's multicore 65nm yield is still miserably low, what is the difference?. However, because of the extra processing, SOI wafers cost about two times the price of bulk silicon. So, AMD needs smaller cores than Intel's buks requires. Or, AMD simply goes to console markets with a 3 core design like Xbox?
Ruiz: We now have a broad spectrum of products that covers every single segment of the market. We’ve done that with 10 percent of the people [that Intel has] and 10 percent of the resources. We have a manufacturing organization that’s benchmarked by Sematech as the best in the industry. I think we’re an innovative company that’s very strong on execution. The fact that we’re six months late with Barcelona seems to overshadow everything else. But if you put that delay aside, that’s why it’s critical for us to continue to gain share—to get to that scale where all of that will become obvious and the there is strength in the financial numbers behind it. We’re pretty close and I’m confident we will do that.
Ruiz: We now have a broad spectrum of products that covers every single segment of the market. We’ve done that with 10 percent of the people [that Intel has] and 10 percent of the resources. We have a manufacturing organization that’s benchmarked by Sematech as the best in the industry. I think we’re an innovative company that’s very strong on execution. The fact that we’re six months late with Barcelona seems to overshadow everything else. But if you put that delay aside, that’s why it’s critical for us to continue to gain share—to get to that scale where all of that will become obvious and the there is strength in the financial numbers behind it. We’re pretty close and I’m confident we will do that.AMD sells 15K Barcelonas for the world fastest computer
How NDA haters will now deny this?
Broken recently at Bad Hardware article. Its 400 Tflops version is announced here. With 13K processors - 4 core Barcelonas . Consequently, Sun acquired Lustre with theirs parallel file system for that purpose. Though , hmm, Sun has their own Petabytes range file system.
New Batman arrives. Oh Gosh, you will like it
Oh I could only imagine unimaginable missuses of this wehicle.
Beside, I am curious, how fast you have to run to take off at all? Where is the place for the parachute?
Chrysler, Honda call back 482K vehicles after the breaks problems
AMD seems to want to spoil the IDF jamboree next week ,
but only if people sign pesky NDAs.
As Bad Hardware has constantly informed you, obviously that AMD has something striking under NDA. Something, that we will anyway see soon. Believe me, I am not under NDA.
And let me remind you that once distinguished The Inquirer made its glory (and harvested our sympathies) with breaking stories BEFORE IDF events. Now it is happy to report from IDF, as anyone can. What a journalism.
As Bad Hardware has constantly informed you, obviously that AMD has something striking under NDA. Something, that we will anyway see soon. Believe me, I am not under NDA.And let me remind you that once distinguished The Inquirer made its glory (and harvested our sympathies) with breaking stories BEFORE IDF events. Now it is happy to report from IDF, as anyone can. What a journalism.
Friday, September 14, 2007
Some Barcelona cores already run at 3.2 Ghz
Thus, some performance benchmarks lose its validity, as clock now isn't fixed any more, as it used to be in the previous AMD generations.
Official list of some currently supported Barcelona features
As you see, still no DRAM unganging support. And no DDR3 support, as some people reports. As of 8.09.2007. Now if Barcelona with registered DDR2 at 800 MT/s dwarfs all Xeons at SPEC_rate_base2006 , what will do with faster and unganged memory support?
Painkiller medicine kills 4 people !
Fentora killed four people, among whom two patients used the medication for headache.
Now, that way cured, they are definitely without any pains ! That is called truthful commercial, regarding to some others unfulfilled promises and hopes. We best remember form hardware gladiators arena. Of course, if you have seemingly unstoppable hardware glitches, try Fentora. Why not. It delivers what it promises. And it could rid you off all the headaches. Forever.
